OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_57/] [or1ksim/] [cpu/] - Rev 1778

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
1353 Modularise simulator command parsing nogj 7076d 20h /or1k/tags/nog_patch_57/or1ksim/cpu/
1352 Optimise execution history tracking nogj 7076d 20h /or1k/tags/nog_patch_57/or1ksim/cpu/
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7076d 21h /or1k/tags/nog_patch_57/or1ksim/cpu/
1346 Remove the global op structure nogj 7090d 00h /or1k/tags/nog_patch_57/or1ksim/cpu/
1345 Fix out-of-tree builds nogj 7090d 00h /or1k/tags/nog_patch_57/or1ksim/cpu/
1344 * Avoid doing a store in *every* instruction executed by storeing the instruction function unit in or32_opcodes nogj 7090d 00h /or1k/tags/nog_patch_57/or1ksim/cpu/
1343 * Fix warnings in insnset.c and execute.c nogj 7090d 01h /or1k/tags/nog_patch_57/or1ksim/cpu/
1342 * Fix generate.c to produce a execgen.c with less warnings.
* Fix the --enable-simple configure option.
nogj 7090d 01h /or1k/tags/nog_patch_57/or1ksim/cpu/
1341 Mark wich operand is the destination operand in the architechture definition nogj 7090d 01h /or1k/tags/nog_patch_57/or1ksim/cpu/
1338 l.ff1 instruction added andreje 7105d 23h /or1k/tags/nog_patch_57/or1ksim/cpu/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.