URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel-0-3-0-rc2/] [or1ksim/] [cpu/] - Rev 431

Rev	Log message	Author	Age	Path
349	Some bugs regarding cache simulation fixed.	simons	8275d 19h	/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
344	added acv test for uart; sim debug now has verbose levels; lot of bugs fixed in uart model	markom	8278d 03h	/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
327	simulate_dc_mmu_load() was calling insn cache/mmu routines instead of data cache/mmu. Fixed.	lampret	8280d 13h	/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
309	more tests run; added cfg capabilities for tests	markom	8284d 00h	/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
308	testbench now has make check	markom	8284d 01h	/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
306	corrected lots of bugs	markom	8284d 05h	/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
304	included VAPI in execution, but it is still not functioning; some cleanup in toplevel.c	markom	8284d 07h	/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
303	Fixed reset exception (ESR0) and added some SPRs to executed.log	lampret	8284d 18h	/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
297	mc +& bug fixed	markom	8285d 04h	/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
296	Sections loaded by physical add.	simons	8285d 05h	/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/