URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_1/] [or1200/] [rtl/] [verilog/] - Rev 1780

Rev	Log message	Author	Age	Path
663	No longer using async rst as sync reset for the counter.	lampret	8179d 12h	/or1k/tags/rel_1/or1200/rtl/verilog/
660	Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.	lampret	8180d 09h	/or1k/tags/rel_1/or1200/rtl/verilog/
636	Fixed combinational loops.	lampret	8189d 18h	/or1k/tags/rel_1/or1200/rtl/verilog/
617	Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.	lampret	8194d 12h	/or1k/tags/rel_1/or1200/rtl/verilog/
610	Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.	lampret	8199d 06h	/or1k/tags/rel_1/or1200/rtl/verilog/
597	Fixed OR1200_XILINX_RAM32X1D.	lampret	8202d 23h	/or1k/tags/rel_1/or1200/rtl/verilog/
596	SR[TEE] should be zero after reset.	lampret	8203d 04h	/or1k/tags/rel_1/or1200/rtl/verilog/
595	Fixed 'the NPC single-step fix'.	lampret	8203d 23h	/or1k/tags/rel_1/or1200/rtl/verilog/
589	No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.	lampret	8204d 06h	/or1k/tags/rel_1/or1200/rtl/verilog/
573	Fixed module name when compiling with OR1200_XILINX_RAM32X1D	lampret	8207d 07h	/or1k/tags/rel_1/or1200/rtl/verilog/