URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_1/] [or1200/] [rtl/] [verilog/] - Rev 668

Rev	Log message	Author	Age	Path
400	force_dslot_fetch does not work - allways zero.	simons	8259d 23h	/or1k/tags/rel_1/or1200/rtl/verilog/
399	Trap insn couses break after exits ex_insn.	simons	8259d 23h	/or1k/tags/rel_1/or1200/rtl/verilog/
391	Fixed except_stop width and fixed EX PC for 1400444f no-ops.	lampret	8262d 19h	/or1k/tags/rel_1/or1200/rtl/verilog/
390	Changed instantiation name of VS RAMs.	lampret	8262d 21h	/or1k/tags/rel_1/or1200/rtl/verilog/
387	Now FPGA and ASIC target are separate.	lampret	8262d 22h	/or1k/tags/rel_1/or1200/rtl/verilog/
386	Fixed VS RAM instantiation - again.	lampret	8262d 22h	/or1k/tags/rel_1/or1200/rtl/verilog/
370	Program counter divided to PPC and NPC.	simons	8266d 20h	/or1k/tags/rel_1/or1200/rtl/verilog/
367	Changed DSR/DRR behavior and exception detection.	lampret	8267d 09h	/or1k/tags/rel_1/or1200/rtl/verilog/
365	Added wb_cyc_o assignment after it was removed by accident.	lampret	8268d 04h	/or1k/tags/rel_1/or1200/rtl/verilog/
360	Added OR1200_REGISTERED_INPUTS.	lampret	8269d 20h	/or1k/tags/rel_1/or1200/rtl/verilog/