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[/] [or1k/] [tags/] [rel_11/] [or1200/] - Rev 1132

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1035 Added optional l.div/l.divu insns. By default they are disabled. lampret 7953d 09h /or1k/tags/rel_11/or1200/
1033 If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY]. lampret 7953d 19h /or1k/tags/rel_11/or1200/
1032 Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS. lampret 7954d 09h /or1k/tags/rel_11/or1200/
1023 Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v. lampret 7957d 14h /or1k/tags/rel_11/or1200/
1022 As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. lampret 7957d 16h /or1k/tags/rel_11/or1200/
1011 Removed some commented RTL. Fixed SR/ESR flag bug. lampret 7964d 13h /or1k/tags/rel_11/or1200/
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 7970d 12h /or1k/tags/rel_11/or1200/
993 Fixed IMMU bug. lampret 7970d 12h /or1k/tags/rel_11/or1200/
984 Disable SB until it is tested lampret 7973d 17h /or1k/tags/rel_11/or1200/
977 Added store buffer. lampret 7973d 19h /or1k/tags/rel_11/or1200/

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