OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_15/] - Rev 1174

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
1148 *** empty log message *** phoenix 7742d 23h /or1k/tags/rel_15/
1147 remove unneeded include phoenix 7742d 23h /or1k/tags/rel_15/
1146 cygwin fix phoenix 7742d 23h /or1k/tags/rel_15/
1145 1) Fix trivial bug w/ transmitter empty interrupts that I introduced in the
last check-in.
2) Improve printed output from debugging-only uart_status() routine.
sfurman 7742d 23h /or1k/tags/rel_15/
1144 Speed up gdb when running with serial targets:

When generating backtraces, the prologue of each function is scanned
at least three times by architecture-independent code, e.g. to
determine offsets of saved registers, identify frameless functions,
etc. This new code adds straightforward caching of the information
gleaned by or1k_scan_prologue() on a per-frame basis rather than
storing it in global static variables. (This benefits both JTAG and
serial gdb targets, though the JTAG target runs fast enough that it is
not particularly needed.)

When the register set is dumped by the serial target, e.g. at any
breakpoint or interrupt, the 32 vector/FP registers were included in
the dump (each 8 bytes long), though they aren't implemented. The new
code tells gdb that unimplemented registers have zero length in the
dump.
sfurman 7745d 05h /or1k/tags/rel_15/
1143 Make UART transmitter-empty interrupts match both 16450 and 16550 behavior. sfurman 7745d 20h /or1k/tags/rel_15/
1142 Speed up gdb when running with serial targets:

When generating backtraces, the prologue of each function is scanned
at least three times by architecture-independent code, e.g. to
determine offsets of saved registers, identify frameless functions,
etc. This new code adds straightforward caching of the information
gleaned by or1k_scan_prologue() on a per-frame basis rather than
storing it in global static variables. (This benefits both JTAG and
serial gdb targets, though the JTAG target runs fast enough that it is
not particularly needed.)

When the register set is dumped by the serial target, e.g. at any
breakpoint or interrupt, the 32 vector/FP registers were included in
the dump (each 8 bytes long), though they aren't implemented. The new
code tells gdb that unimplemented registers have zero length in the
dump.
sfurman 7745d 20h /or1k/tags/rel_15/
1141 WB = 1/2 RISC clock test code enabled. lampret 7747d 05h /or1k/tags/rel_15/
1140 Fixed OR1200_CLKDIV_x_SUPPORTED defines. Fixed order of ifdefs. lampret 7747d 05h /or1k/tags/rel_15/
1139 Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description. lampret 7747d 05h /or1k/tags/rel_15/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.