OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_16/] [or1200/] - Rev 1782

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
1112 Updated sensitivity list for trace buffer [only relevant for Xilinx FPGAs] lampret 7807d 19h /or1k/tags/rel_16/or1200/
1104 Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional. lampret 7852d 13h /or1k/tags/rel_16/or1200/
1083 SB mem width fixed. simons 7884d 08h /or1k/tags/rel_16/or1200/
1079 RAMs wrong connected to the BIST scan chain. mohor 7893d 06h /or1k/tags/rel_16/or1200/
1078 Previous check-in was done by mistake. mohor 7893d 07h /or1k/tags/rel_16/or1200/
1077 Signal scanb_sen renamed to scanb_en. mohor 7893d 07h /or1k/tags/rel_16/or1200/
1069 Signal scanb_eni renamed to scanb_en mohor 7897d 00h /or1k/tags/rel_16/or1200/
1063 Added BIST scan. Special VS RAMs need to be used to implement BIST. lampret 7904d 02h /or1k/tags/rel_16/or1200/
1055 Removed obsolete comment. lampret 7935d 19h /or1k/tags/rel_16/or1200/
1054 Fixed a combinational loop. lampret 7935d 19h /or1k/tags/rel_16/or1200/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.