URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_16/] [or1200/] [rtl/] - Rev 737

Rev	Log message	Author	Age	Path
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8257d 14h	/or1k/tags/rel_16/or1200/rtl/
402	Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32	lampret	8287d 17h	/or1k/tags/rel_16/or1200/rtl/
401	* empty log message *	simons	8291d 03h	/or1k/tags/rel_16/or1200/rtl/
400	force_dslot_fetch does not work - allways zero.	simons	8291d 03h	/or1k/tags/rel_16/or1200/rtl/
399	Trap insn couses break after exits ex_insn.	simons	8291d 03h	/or1k/tags/rel_16/or1200/rtl/
391	Fixed except_stop width and fixed EX PC for 1400444f no-ops.	lampret	8293d 23h	/or1k/tags/rel_16/or1200/rtl/
390	Changed instantiation name of VS RAMs.	lampret	8294d 01h	/or1k/tags/rel_16/or1200/rtl/
387	Now FPGA and ASIC target are separate.	lampret	8294d 03h	/or1k/tags/rel_16/or1200/rtl/
386	Fixed VS RAM instantiation - again.	lampret	8294d 03h	/or1k/tags/rel_16/or1200/rtl/
370	Program counter divided to PPC and NPC.	simons	8298d 01h	/or1k/tags/rel_16/or1200/rtl/