URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_16/] [or1200/] [rtl/] [verilog/] - Rev 775

Rev	Log message	Author	Age	Path
536	Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be.	lampret	8239d 12h	/or1k/tags/rel_16/or1200/rtl/verilog/
512	Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target.	lampret	8243d 16h	/or1k/tags/rel_16/or1200/rtl/verilog/
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8244d 05h	/or1k/tags/rel_16/or1200/rtl/verilog/
402	Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32	lampret	8274d 08h	/or1k/tags/rel_16/or1200/rtl/verilog/
401	* empty log message *	simons	8277d 18h	/or1k/tags/rel_16/or1200/rtl/verilog/
400	force_dslot_fetch does not work - allways zero.	simons	8277d 18h	/or1k/tags/rel_16/or1200/rtl/verilog/
399	Trap insn couses break after exits ex_insn.	simons	8277d 18h	/or1k/tags/rel_16/or1200/rtl/verilog/
391	Fixed except_stop width and fixed EX PC for 1400444f no-ops.	lampret	8280d 14h	/or1k/tags/rel_16/or1200/rtl/verilog/
390	Changed instantiation name of VS RAMs.	lampret	8280d 16h	/or1k/tags/rel_16/or1200/rtl/verilog/
387	Now FPGA and ASIC target are separate.	lampret	8280d 18h	/or1k/tags/rel_16/or1200/rtl/verilog/