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[/] [or1k/] [tags/] [rel_18/] [or1200/] - Rev 1782

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Rev Log message Author Age Path
1130 RFRAM type always need to be defined. lampret 7739d 16h /or1k/tags/rel_18/or1200/
1129 Added Altera LPM RAMs. Changed generic RAM output when OE inactive. lampret 7739d 16h /or1k/tags/rel_18/or1200/
1112 Updated sensitivity list for trace buffer [only relevant for Xilinx FPGAs] lampret 7814d 14h /or1k/tags/rel_18/or1200/
1104 Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional. lampret 7859d 08h /or1k/tags/rel_18/or1200/
1083 SB mem width fixed. simons 7891d 03h /or1k/tags/rel_18/or1200/
1079 RAMs wrong connected to the BIST scan chain. mohor 7900d 01h /or1k/tags/rel_18/or1200/
1078 Previous check-in was done by mistake. mohor 7900d 02h /or1k/tags/rel_18/or1200/
1077 Signal scanb_sen renamed to scanb_en. mohor 7900d 02h /or1k/tags/rel_18/or1200/
1069 Signal scanb_eni renamed to scanb_en mohor 7903d 19h /or1k/tags/rel_18/or1200/
1063 Added BIST scan. Special VS RAMs need to be used to implement BIST. lampret 7910d 21h /or1k/tags/rel_18/or1200/

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