URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_2/] [or1200/] [rtl/] - Rev 958

Rev	Log message	Author	Age	Path
736	Changed generation of SPR address. Now it is ORed from base and offset instead of a sum.	lampret	8138d 11h	/or1k/tags/rel_2/or1200/rtl/
735	Fixed async loop. Changed multiplier type for ASIC.	lampret	8138d 11h	/or1k/tags/rel_2/or1200/rtl/
668	Lapsus fixed.	simons	8162d 21h	/or1k/tags/rel_2/or1200/rtl/
663	No longer using async rst as sync reset for the counter.	lampret	8165d 11h	/or1k/tags/rel_2/or1200/rtl/
660	Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.	lampret	8166d 08h	/or1k/tags/rel_2/or1200/rtl/
636	Fixed combinational loops.	lampret	8175d 16h	/or1k/tags/rel_2/or1200/rtl/
617	Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.	lampret	8180d 11h	/or1k/tags/rel_2/or1200/rtl/
610	Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.	lampret	8185d 04h	/or1k/tags/rel_2/or1200/rtl/
597	Fixed OR1200_XILINX_RAM32X1D.	lampret	8188d 22h	/or1k/tags/rel_2/or1200/rtl/
596	SR[TEE] should be zero after reset.	lampret	8189d 03h	/or1k/tags/rel_2/or1200/rtl/