URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_20/] - Rev 1154

Rev	Log message	Author	Age	Path
1134	Changed location of debug test code to 0.	lampret	7741d 20h	/or1k/tags/rel_20/
1133	Adding OR1200_CLMODE_1TO2 test code.	lampret	7741d 20h	/or1k/tags/rel_20/
1132	RFRAM defines comments updated. Altera LPM option added.	lampret	7741d 20h	/or1k/tags/rel_20/
1131	Added another pipe stage to match gmult. One day second pipe in amult and gmult might be removed to get better performance.	lampret	7741d 20h	/or1k/tags/rel_20/
1130	RFRAM type always need to be defined.	lampret	7741d 20h	/or1k/tags/rel_20/
1129	Added Altera LPM RAMs. Changed generic RAM output when OE inactive.	lampret	7741d 20h	/or1k/tags/rel_20/
1128	Fixed my bustage: Add missing 2nd argument to open(). Otherwise, opening a serial port channel can sporadically fail.	sfurman	7746d 19h	/or1k/tags/rel_20/
1127	Added ability to map I/O from simulated UARTs to physical serial ports on the host running the simulator.	sfurman	7749d 20h	/or1k/tags/rel_20/
1126	Added lengthy comment explaining all possible choices for UART channels, e.g. xterm, tcp, file, etc.	sfurman	7751d 22h	/or1k/tags/rel_20/
1125	This test case passes.	lampret	7763d 02h	/or1k/tags/rel_20/