OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_21/] [or1200/] - Rev 1783

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
1155 No functional change. Only added customization for exception vectors. lampret 7722d 15h /or1k/tags/rel_21/or1200/
1140 Fixed OR1200_CLKDIV_x_SUPPORTED defines. Fixed order of ifdefs. lampret 7735d 17h /or1k/tags/rel_21/or1200/
1139 Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description. lampret 7735d 17h /or1k/tags/rel_21/or1200/
1132 RFRAM defines comments updated. Altera LPM option added. lampret 7736d 12h /or1k/tags/rel_21/or1200/
1131 Added another pipe stage to match gmult. One day second pipe in amult and gmult might be removed to get better performance. lampret 7736d 12h /or1k/tags/rel_21/or1200/
1130 RFRAM type always need to be defined. lampret 7736d 12h /or1k/tags/rel_21/or1200/
1129 Added Altera LPM RAMs. Changed generic RAM output when OE inactive. lampret 7736d 12h /or1k/tags/rel_21/or1200/
1112 Updated sensitivity list for trace buffer [only relevant for Xilinx FPGAs] lampret 7811d 10h /or1k/tags/rel_21/or1200/
1104 Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional. lampret 7856d 05h /or1k/tags/rel_21/or1200/
1083 SB mem width fixed. simons 7888d 00h /or1k/tags/rel_21/or1200/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.