URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_21/] [or1200/] [rtl/] - Rev 636

Rev	Log message	Author	Age	Path
390	Changed instantiation name of VS RAMs.	lampret	8263d 19h	/or1k/tags/rel_21/or1200/rtl/
387	Now FPGA and ASIC target are separate.	lampret	8263d 21h	/or1k/tags/rel_21/or1200/rtl/
386	Fixed VS RAM instantiation - again.	lampret	8263d 21h	/or1k/tags/rel_21/or1200/rtl/
370	Program counter divided to PPC and NPC.	simons	8267d 19h	/or1k/tags/rel_21/or1200/rtl/
367	Changed DSR/DRR behavior and exception detection.	lampret	8268d 08h	/or1k/tags/rel_21/or1200/rtl/
365	Added wb_cyc_o assignment after it was removed by accident.	lampret	8269d 03h	/or1k/tags/rel_21/or1200/rtl/
360	Added OR1200_REGISTERED_INPUTS.	lampret	8270d 19h	/or1k/tags/rel_21/or1200/rtl/
359	Added optional sampling of inputs.	lampret	8270d 19h	/or1k/tags/rel_21/or1200/rtl/
358	Fixed virtual silicon single-port rams instantiation.	lampret	8270d 19h	/or1k/tags/rel_21/or1200/rtl/
357	Fixed dbg_is_o assignment width.	lampret	8270d 19h	/or1k/tags/rel_21/or1200/rtl/