URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_21/] [or1200/] [rtl/] [verilog/] - Rev 1139

Rev	Log message	Author	Age	Path
1023	Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v.	lampret	7983d 01h	/or1k/tags/rel_21/or1200/rtl/verilog/
1022	As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.	lampret	7983d 03h	/or1k/tags/rel_21/or1200/rtl/verilog/
1011	Removed some commented RTL. Fixed SR/ESR flag bug.	lampret	7990d 00h	/or1k/tags/rel_21/or1200/rtl/verilog/
994	Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.	lampret	7995d 23h	/or1k/tags/rel_21/or1200/rtl/verilog/
993	Fixed IMMU bug.	lampret	7995d 23h	/or1k/tags/rel_21/or1200/rtl/verilog/
984	Disable SB until it is tested	lampret	7999d 03h	/or1k/tags/rel_21/or1200/rtl/verilog/
977	Added store buffer.	lampret	7999d 06h	/or1k/tags/rel_21/or1200/rtl/verilog/
962	Fixed Xilinx trace buffer address. REported by Taylor Su.	lampret	8002d 19h	/or1k/tags/rel_21/or1200/rtl/verilog/
958	Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run.	lampret	8003d 19h	/or1k/tags/rel_21/or1200/rtl/verilog/
944	Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section.	lampret	8005d 20h	/or1k/tags/rel_21/or1200/rtl/verilog/