URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_21/] [or1200/] [rtl/] [verilog/] - Rev 1188

Rev	Log message	Author	Age	Path
1063	Added BIST scan. Special VS RAMs need to be used to implement BIST.	lampret	7974d 05h	/or1k/tags/rel_21/or1200/rtl/verilog/
1055	Removed obsolete comment.	lampret	8005d 22h	/or1k/tags/rel_21/or1200/rtl/verilog/
1054	Fixed a combinational loop.	lampret	8005d 22h	/or1k/tags/rel_21/or1200/rtl/verilog/
1053	Disabled cache inhibit atttribute.	lampret	8005d 22h	/or1k/tags/rel_21/or1200/rtl/verilog/
1038	Fixed a typo, reported by Taylor Su.	lampret	8013d 06h	/or1k/tags/rel_21/or1200/rtl/verilog/
1035	Added optional l.div/l.divu insns. By default they are disabled.	lampret	8013d 20h	/or1k/tags/rel_21/or1200/rtl/verilog/
1033	If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].	lampret	8014d 06h	/or1k/tags/rel_21/or1200/rtl/verilog/
1032	Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.	lampret	8014d 20h	/or1k/tags/rel_21/or1200/rtl/verilog/
1023	Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v.	lampret	8018d 01h	/or1k/tags/rel_21/or1200/rtl/verilog/
1022	As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.	lampret	8018d 03h	/or1k/tags/rel_21/or1200/rtl/verilog/