URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_25/] [or1200/] [rtl/] [verilog/] - Rev 1129

Rev	Log message	Author	Age	Path
993	Fixed IMMU bug.	lampret	7995d 13h	/or1k/tags/rel_25/or1200/rtl/verilog/
984	Disable SB until it is tested	lampret	7998d 17h	/or1k/tags/rel_25/or1200/rtl/verilog/
977	Added store buffer.	lampret	7998d 19h	/or1k/tags/rel_25/or1200/rtl/verilog/
962	Fixed Xilinx trace buffer address. REported by Taylor Su.	lampret	8002d 09h	/or1k/tags/rel_25/or1200/rtl/verilog/
958	Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run.	lampret	8003d 08h	/or1k/tags/rel_25/or1200/rtl/verilog/
944	Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section.	lampret	8005d 09h	/or1k/tags/rel_25/or1200/rtl/verilog/
943	Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers.	lampret	8005d 09h	/or1k/tags/rel_25/or1200/rtl/verilog/
942	Delayed external access at page crossing.	lampret	8005d 09h	/or1k/tags/rel_25/or1200/rtl/verilog/
916	MAC now follows software convention (signed multiply instead of unsigned).	lampret	8017d 13h	/or1k/tags/rel_25/or1200/rtl/verilog/
895	Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.	lampret	8033d 17h	/or1k/tags/rel_25/or1200/rtl/verilog/