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Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] - Rev 1063

Rev	Log message	Author	Age	Path
916	MAC now follows software convention (signed multiply instead of unsigned).	lampret	8021d 19h	/or1k/tags/rel_26/or1200/rtl/verilog/
895	Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.	lampret	8037d 23h	/or1k/tags/rel_26/or1200/rtl/verilog/
871	Generic flip-flop based memory macro for register file.	lampret	8074d 05h	/or1k/tags/rel_26/or1200/rtl/verilog/
870	Added defines for enabling generic FF based memory macro for register file.	lampret	8074d 05h	/or1k/tags/rel_26/or1200/rtl/verilog/
869	Added generic flip-flop based memory macro instantiation.	lampret	8074d 05h	/or1k/tags/rel_26/or1200/rtl/verilog/
795	Added a directive to ignore signed division variables that are only used in simulation.	lampret	8145d 04h	/or1k/tags/rel_26/or1200/rtl/verilog/
794	Added again just recently removed full_case directive	lampret	8145d 04h	/or1k/tags/rel_26/or1200/rtl/verilog/
791	Fixed some ports in instnatiations that were removed from the modules	lampret	8145d 05h	/or1k/tags/rel_26/or1200/rtl/verilog/
790	Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives	lampret	8145d 05h	/or1k/tags/rel_26/or1200/rtl/verilog/
788	Some of the warnings fixed.	lampret	8145d 06h	/or1k/tags/rel_26/or1200/rtl/verilog/