URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_27/] [or1200/] [rtl/] - Rev 1055

Rev	Log message	Author	Age	Path
895	Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.	lampret	8030d 13h	/or1k/tags/rel_27/or1200/rtl/
871	Generic flip-flop based memory macro for register file.	lampret	8066d 18h	/or1k/tags/rel_27/or1200/rtl/
870	Added defines for enabling generic FF based memory macro for register file.	lampret	8066d 19h	/or1k/tags/rel_27/or1200/rtl/
869	Added generic flip-flop based memory macro instantiation.	lampret	8066d 19h	/or1k/tags/rel_27/or1200/rtl/
795	Added a directive to ignore signed division variables that are only used in simulation.	lampret	8137d 18h	/or1k/tags/rel_27/or1200/rtl/
794	Added again just recently removed full_case directive	lampret	8137d 18h	/or1k/tags/rel_27/or1200/rtl/
791	Fixed some ports in instnatiations that were removed from the modules	lampret	8137d 18h	/or1k/tags/rel_27/or1200/rtl/
790	Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives	lampret	8137d 18h	/or1k/tags/rel_27/or1200/rtl/
788	Some of the warnings fixed.	lampret	8137d 20h	/or1k/tags/rel_27/or1200/rtl/
778	Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.	lampret	8138d 15h	/or1k/tags/rel_27/or1200/rtl/