URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_27/] [or1200/] [rtl/] - Rev 1778

Rev	Log message	Author	Age	Path
1131	Added another pipe stage to match gmult. One day second pipe in amult and gmult might be removed to get better performance.	lampret	7749d 11h	/or1k/tags/rel_27/or1200/rtl/
1130	RFRAM type always need to be defined.	lampret	7749d 11h	/or1k/tags/rel_27/or1200/rtl/
1129	Added Altera LPM RAMs. Changed generic RAM output when OE inactive.	lampret	7749d 11h	/or1k/tags/rel_27/or1200/rtl/
1112	Updated sensitivity list for trace buffer [only relevant for Xilinx FPGAs]	lampret	7824d 09h	/or1k/tags/rel_27/or1200/rtl/
1104	Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.	lampret	7869d 03h	/or1k/tags/rel_27/or1200/rtl/
1083	SB mem width fixed.	simons	7900d 22h	/or1k/tags/rel_27/or1200/rtl/
1079	RAMs wrong connected to the BIST scan chain.	mohor	7909d 20h	/or1k/tags/rel_27/or1200/rtl/
1078	Previous check-in was done by mistake.	mohor	7909d 21h	/or1k/tags/rel_27/or1200/rtl/
1077	Signal scanb_sen renamed to scanb_en.	mohor	7909d 21h	/or1k/tags/rel_27/or1200/rtl/
1069	Signal scanb_eni renamed to scanb_en	mohor	7913d 14h	/or1k/tags/rel_27/or1200/rtl/