URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_27/] [or1200/] [rtl/] - Rev 870

Rev	Log message	Author	Age	Path
610	Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.	lampret	8228d 00h	/or1k/tags/rel_27/or1200/rtl/
597	Fixed OR1200_XILINX_RAM32X1D.	lampret	8231d 17h	/or1k/tags/rel_27/or1200/rtl/
596	SR[TEE] should be zero after reset.	lampret	8231d 22h	/or1k/tags/rel_27/or1200/rtl/
595	Fixed 'the NPC single-step fix'.	lampret	8232d 17h	/or1k/tags/rel_27/or1200/rtl/
589	No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.	lampret	8233d 00h	/or1k/tags/rel_27/or1200/rtl/
573	Fixed module name when compiling with OR1200_XILINX_RAM32X1D	lampret	8236d 01h	/or1k/tags/rel_27/or1200/rtl/
571	Changed alignment exception EPCR. Not tested yet.	lampret	8236d 10h	/or1k/tags/rel_27/or1200/rtl/
570	Fixed order of syscall and range exceptions.	lampret	8236d 12h	/or1k/tags/rel_27/or1200/rtl/
569	Default ASIC configuration does not sample WB inputs.	lampret	8236d 22h	/or1k/tags/rel_27/or1200/rtl/
562	Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.	lampret	8237d 01h	/or1k/tags/rel_27/or1200/rtl/