URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_28/] - Rev 1241

Rev	Log message	Author	Age	Path
1193	disabled SRAM_GENERIC and added comment + corrected 'wb_err' into 'wb_err_o'	dries	7613d 05h	/or1k/tags/rel_28/
1192	disabled 'bench_defines.v' during synthesis + added define to specify usage of flash instruction address	dries	7613d 07h	/or1k/tags/rel_28/
1191	disabled 'bench_defines.v' during synthesis + added define to specify usage of flash instruction address	dries	7613d 07h	/or1k/tags/rel_28/
1188	Added support for rams with byte write access.	simons	7629d 05h	/or1k/tags/rel_28/
1186	Added support for rams with byte write access.	simons	7630d 04h	/or1k/tags/rel_28/
1184	Scan signals mess fixed.	simons	7636d 21h	/or1k/tags/rel_28/
1183	OpenRISC port of gdb-5.3 straightforwardly derived from gdb-5.0	sfurman	7641d 13h	/or1k/tags/rel_28/
1181	Initial import of unmodified gdb-5.3 source on vendor branch	sfurman	7641d 15h	/or1k/tags/rel_28/
1179	BIST interface added for Artisan memory instances.	simons	7645d 00h	/or1k/tags/rel_28/
1178	avoid another immu exception that should not happen	phoenix	7674d 12h	/or1k/tags/rel_28/