URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_29/] [or1200/] [rtl/] [verilog/] - Rev 402

Rev	Log message	Author	Age	Path
350	For GDB changed single stepping and disabled trap exception.	lampret	8269d 17h	/or1k/tags/rel_29/or1200/rtl/verilog/
338	Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)	lampret	8274d 15h	/or1k/tags/rel_29/or1200/rtl/verilog/
337	Fixed tick timer interrupt reporting by using TTCR[IP] bit.	lampret	8274d 15h	/or1k/tags/rel_29/or1200/rtl/verilog/
328	Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.	lampret	8276d 00h	/or1k/tags/rel_29/or1200/rtl/verilog/
316	Fixed exceptions.	lampret	8277d 22h	/or1k/tags/rel_29/or1200/rtl/verilog/
271	Added missing endif	lampret	8282d 11h	/or1k/tags/rel_29/or1200/rtl/verilog/
265	Modified virtual silicon instantiations.	lampret	8285d 06h	/or1k/tags/rel_29/or1200/rtl/verilog/
220	Fixed parameters in generic sprams.	lampret	8296d 06h	/or1k/tags/rel_29/or1200/rtl/verilog/
219	Fixed sensitivity list.	lampret	8297d 07h	/or1k/tags/rel_29/or1200/rtl/verilog/
218	Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.	lampret	8297d 07h	/or1k/tags/rel_29/or1200/rtl/verilog/