URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_3/] [or1200/] [rtl/] [verilog/] - Rev 504

Rev	Log message	Author	Age	Path
351	Fixed some l.trap typos.	lampret	8261d 02h	/or1k/tags/rel_3/or1200/rtl/verilog/
350	For GDB changed single stepping and disabled trap exception.	lampret	8261d 03h	/or1k/tags/rel_3/or1200/rtl/verilog/
338	Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)	lampret	8266d 02h	/or1k/tags/rel_3/or1200/rtl/verilog/
337	Fixed tick timer interrupt reporting by using TTCR[IP] bit.	lampret	8266d 02h	/or1k/tags/rel_3/or1200/rtl/verilog/
328	Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.	lampret	8267d 10h	/or1k/tags/rel_3/or1200/rtl/verilog/
316	Fixed exceptions.	lampret	8269d 08h	/or1k/tags/rel_3/or1200/rtl/verilog/
271	Added missing endif	lampret	8273d 21h	/or1k/tags/rel_3/or1200/rtl/verilog/
265	Modified virtual silicon instantiations.	lampret	8276d 17h	/or1k/tags/rel_3/or1200/rtl/verilog/
220	Fixed parameters in generic sprams.	lampret	8287d 16h	/or1k/tags/rel_3/or1200/rtl/verilog/
219	Fixed sensitivity list.	lampret	8288d 18h	/or1k/tags/rel_3/or1200/rtl/verilog/