OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_4/] [or1200/] - Rev 1781

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
791 Fixed some ports in instnatiations that were removed from the modules lampret 8135d 18h /or1k/tags/rel_4/or1200/
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8135d 18h /or1k/tags/rel_4/or1200/
788 Some of the warnings fixed. lampret 8135d 20h /or1k/tags/rel_4/or1200/
778 Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. lampret 8136d 15h /or1k/tags/rel_4/or1200/
777 Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2 lampret 8136d 16h /or1k/tags/rel_4/or1200/
776 Updated defines. lampret 8136d 16h /or1k/tags/rel_4/or1200/
775 Optimized cache controller FSM. lampret 8136d 16h /or1k/tags/rel_4/or1200/
774 Removed old files. lampret 8136d 16h /or1k/tags/rel_4/or1200/
737 Added alternative for critical path in DU. lampret 8151d 10h /or1k/tags/rel_4/or1200/
736 Changed generation of SPR address. Now it is ORed from base and offset instead of a sum. lampret 8154d 09h /or1k/tags/rel_4/or1200/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.