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[/] [or1k/] [tags/] [rel_5/] [or1200/] - Rev 774

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Rev Log message Author Age Path
512 Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target. lampret 8210d 02h /or1k/tags/rel_5/or1200/
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8210d 15h /or1k/tags/rel_5/or1200/
402 Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32 lampret 8240d 19h /or1k/tags/rel_5/or1200/
401 *** empty log message *** simons 8244d 05h /or1k/tags/rel_5/or1200/
400 force_dslot_fetch does not work - allways zero. simons 8244d 05h /or1k/tags/rel_5/or1200/
399 Trap insn couses break after exits ex_insn. simons 8244d 05h /or1k/tags/rel_5/or1200/
391 Fixed except_stop width and fixed EX PC for 1400444f no-ops. lampret 8247d 00h /or1k/tags/rel_5/or1200/
390 Changed instantiation name of VS RAMs. lampret 8247d 02h /or1k/tags/rel_5/or1200/
387 Now FPGA and ASIC target are separate. lampret 8247d 04h /or1k/tags/rel_5/or1200/
386 Fixed VS RAM instantiation - again. lampret 8247d 04h /or1k/tags/rel_5/or1200/

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