URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_5/] [or1200/] - Rev 775

Rev	Log message	Author	Age	Path
536	Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be.	lampret	8211d 06h	/or1k/tags/rel_5/or1200/
512	Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target.	lampret	8215d 10h	/or1k/tags/rel_5/or1200/
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8215d 23h	/or1k/tags/rel_5/or1200/
402	Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32	lampret	8246d 02h	/or1k/tags/rel_5/or1200/
401	* empty log message *	simons	8249d 12h	/or1k/tags/rel_5/or1200/
400	force_dslot_fetch does not work - allways zero.	simons	8249d 12h	/or1k/tags/rel_5/or1200/
399	Trap insn couses break after exits ex_insn.	simons	8249d 12h	/or1k/tags/rel_5/or1200/
391	Fixed except_stop width and fixed EX PC for 1400444f no-ops.	lampret	8252d 08h	/or1k/tags/rel_5/or1200/
390	Changed instantiation name of VS RAMs.	lampret	8252d 10h	/or1k/tags/rel_5/or1200/
387	Now FPGA and ASIC target are separate.	lampret	8252d 11h	/or1k/tags/rel_5/or1200/