URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_5/] [or1200/] [rtl/] [verilog/] - Rev 1011

Rev	Log message	Author	Age	Path
778	Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.	lampret	8164d 16h	/or1k/tags/rel_5/or1200/rtl/verilog/
777	Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2	lampret	8164d 16h	/or1k/tags/rel_5/or1200/rtl/verilog/
776	Updated defines.	lampret	8164d 16h	/or1k/tags/rel_5/or1200/rtl/verilog/
775	Optimized cache controller FSM.	lampret	8164d 16h	/or1k/tags/rel_5/or1200/rtl/verilog/
774	Removed old files.	lampret	8164d 16h	/or1k/tags/rel_5/or1200/rtl/verilog/
737	Added alternative for critical path in DU.	lampret	8179d 11h	/or1k/tags/rel_5/or1200/rtl/verilog/
736	Changed generation of SPR address. Now it is ORed from base and offset instead of a sum.	lampret	8182d 10h	/or1k/tags/rel_5/or1200/rtl/verilog/
735	Fixed async loop. Changed multiplier type for ASIC.	lampret	8182d 10h	/or1k/tags/rel_5/or1200/rtl/verilog/
668	Lapsus fixed.	simons	8206d 20h	/or1k/tags/rel_5/or1200/rtl/verilog/
663	No longer using async rst as sync reset for the counter.	lampret	8209d 10h	/or1k/tags/rel_5/or1200/rtl/verilog/