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[/] [or1k/] [tags/] [rel_5/] [or1200/] [rtl/] [verilog/] - Rev 1023

Rev	Log message	Author	Age	Path
790	Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives	lampret	8138d 14h	/or1k/tags/rel_5/or1200/rtl/verilog/
788	Some of the warnings fixed.	lampret	8138d 15h	/or1k/tags/rel_5/or1200/rtl/verilog/
778	Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.	lampret	8139d 11h	/or1k/tags/rel_5/or1200/rtl/verilog/
777	Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2	lampret	8139d 11h	/or1k/tags/rel_5/or1200/rtl/verilog/
776	Updated defines.	lampret	8139d 11h	/or1k/tags/rel_5/or1200/rtl/verilog/
775	Optimized cache controller FSM.	lampret	8139d 11h	/or1k/tags/rel_5/or1200/rtl/verilog/
774	Removed old files.	lampret	8139d 11h	/or1k/tags/rel_5/or1200/rtl/verilog/
737	Added alternative for critical path in DU.	lampret	8154d 05h	/or1k/tags/rel_5/or1200/rtl/verilog/
736	Changed generation of SPR address. Now it is ORed from base and offset instead of a sum.	lampret	8157d 05h	/or1k/tags/rel_5/or1200/rtl/verilog/
735	Fixed async loop. Changed multiplier type for ASIC.	lampret	8157d 05h	/or1k/tags/rel_5/or1200/rtl/verilog/