URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_5/] [or1200/] [rtl/] [verilog/] - Rev 1054

Rev	Log message	Author	Age	Path
871	Generic flip-flop based memory macro for register file.	lampret	8092d 10h	/or1k/tags/rel_5/or1200/rtl/verilog/
870	Added defines for enabling generic FF based memory macro for register file.	lampret	8092d 10h	/or1k/tags/rel_5/or1200/rtl/verilog/
869	Added generic flip-flop based memory macro instantiation.	lampret	8092d 10h	/or1k/tags/rel_5/or1200/rtl/verilog/
795	Added a directive to ignore signed division variables that are only used in simulation.	lampret	8163d 10h	/or1k/tags/rel_5/or1200/rtl/verilog/
794	Added again just recently removed full_case directive	lampret	8163d 10h	/or1k/tags/rel_5/or1200/rtl/verilog/
791	Fixed some ports in instnatiations that were removed from the modules	lampret	8163d 10h	/or1k/tags/rel_5/or1200/rtl/verilog/
790	Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives	lampret	8163d 10h	/or1k/tags/rel_5/or1200/rtl/verilog/
788	Some of the warnings fixed.	lampret	8163d 11h	/or1k/tags/rel_5/or1200/rtl/verilog/
778	Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.	lampret	8164d 07h	/or1k/tags/rel_5/or1200/rtl/verilog/
777	Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2	lampret	8164d 07h	/or1k/tags/rel_5/or1200/rtl/verilog/