URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_6/] [or1200/] - Rev 1765

Rev	Log message	Author	Age	Path
977	Added store buffer.	lampret	7973d 03h	/or1k/tags/rel_6/or1200/
962	Fixed Xilinx trace buffer address. REported by Taylor Su.	lampret	7976d 17h	/or1k/tags/rel_6/or1200/
960	Directory cleanup.	lampret	7976d 17h	/or1k/tags/rel_6/or1200/
958	Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run.	lampret	7977d 17h	/or1k/tags/rel_6/or1200/
944	Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section.	lampret	7979d 17h	/or1k/tags/rel_6/or1200/
943	Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers.	lampret	7979d 17h	/or1k/tags/rel_6/or1200/
942	Delayed external access at page crossing.	lampret	7979d 17h	/or1k/tags/rel_6/or1200/
916	MAC now follows software convention (signed multiply instead of unsigned).	lampret	7991d 21h	/or1k/tags/rel_6/or1200/
895	Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.	lampret	8008d 01h	/or1k/tags/rel_6/or1200/
871	Generic flip-flop based memory macro for register file.	lampret	8044d 07h	/or1k/tags/rel_6/or1200/