URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_7/] [or1200/] [rtl/] [verilog/] - Rev 1765

Rev	Log message	Author	Age	Path
977	Added store buffer.	lampret	7996d 04h	/or1k/tags/rel_7/or1200/rtl/verilog/
962	Fixed Xilinx trace buffer address. REported by Taylor Su.	lampret	7999d 18h	/or1k/tags/rel_7/or1200/rtl/verilog/
958	Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run.	lampret	8000d 17h	/or1k/tags/rel_7/or1200/rtl/verilog/
944	Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section.	lampret	8002d 18h	/or1k/tags/rel_7/or1200/rtl/verilog/
943	Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers.	lampret	8002d 18h	/or1k/tags/rel_7/or1200/rtl/verilog/
942	Delayed external access at page crossing.	lampret	8002d 18h	/or1k/tags/rel_7/or1200/rtl/verilog/
916	MAC now follows software convention (signed multiply instead of unsigned).	lampret	8014d 22h	/or1k/tags/rel_7/or1200/rtl/verilog/
895	Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.	lampret	8031d 01h	/or1k/tags/rel_7/or1200/rtl/verilog/
871	Generic flip-flop based memory macro for register file.	lampret	8067d 07h	/or1k/tags/rel_7/or1200/rtl/verilog/
870	Added defines for enabling generic FF based memory macro for register file.	lampret	8067d 07h	/or1k/tags/rel_7/or1200/rtl/verilog/