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[/] [or1k/] [tags/] [rel_8/] [or1200/] - Rev 1778

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Rev Log message Author Age Path
1022 As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. lampret 7964d 13h /or1k/tags/rel_8/or1200/
1011 Removed some commented RTL. Fixed SR/ESR flag bug. lampret 7971d 09h /or1k/tags/rel_8/or1200/
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 7977d 09h /or1k/tags/rel_8/or1200/
993 Fixed IMMU bug. lampret 7977d 09h /or1k/tags/rel_8/or1200/
984 Disable SB until it is tested lampret 7980d 13h /or1k/tags/rel_8/or1200/
977 Added store buffer. lampret 7980d 15h /or1k/tags/rel_8/or1200/
962 Fixed Xilinx trace buffer address. REported by Taylor Su. lampret 7984d 05h /or1k/tags/rel_8/or1200/
960 Directory cleanup. lampret 7984d 05h /or1k/tags/rel_8/or1200/
958 Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run. lampret 7985d 05h /or1k/tags/rel_8/or1200/
944 Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section. lampret 7987d 06h /or1k/tags/rel_8/or1200/

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