URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_1_0/] [or1ksim/] [cpu/] [or1k/] - Rev 1780

Rev	Log message	Author	Age	Path
1169	Added support for l.addc instruction.	csanchez	7707d 02h	/or1k/tags/stable_0_1_0/or1ksim/cpu/or1k/
1117	Ignore generated files for CVS purposes	sfurman	7830d 22h	/or1k/tags/stable_0_1_0/or1ksim/cpu/or1k/
1106	Cache invalidate bug fixed again (it was ok before).	simons	7911d 05h	/or1k/tags/stable_0_1_0/or1ksim/cpu/or1k/
1097	Cache invalidate bug fixed.	simons	7918d 00h	/or1k/tags/stable_0_1_0/or1ksim/cpu/or1k/
1086	STACK_ARGS is getting obsolete and is only needed by simprintf, which needs it to be 0.	lampret	7924d 20h	/or1k/tags/stable_0_1_0/or1ksim/cpu/or1k/
1025	PRINTF/printf mess fixed.	simons	8007d 01h	/or1k/tags/stable_0_1_0/or1ksim/cpu/or1k/
1024	Mess with printf/PRINTF fixed. Ethernet test changed to support latest changes.	simons	8007d 10h	/or1k/tags/stable_0_1_0/or1ksim/cpu/or1k/
997	PRINTF should be used instead of printf; command redirection repaired	markom	8019d 13h	/or1k/tags/stable_0_1_0/or1ksim/cpu/or1k/
970	Testbench is now running on ORP architecture platform.	simons	8027d 00h	/or1k/tags/stable_0_1_0/or1ksim/cpu/or1k/
914	SR[FO] is always set to 1.	lampret	8043d 12h	/or1k/tags/stable_0_1_0/or1ksim/cpu/or1k/