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[/] [or1k/] [tags/] [stable_0_2_0/] - Rev 1634

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1614 CI should not be set in dMMU translation tables or one gets different behaviour with dMMU on or off in case data cache is enabled. care should be taken for addresses higher than 0x7fff_ffff where the situation is just reversed. (since or1200 does not cache upper half of address space if there is no dMMU) phoenix 6797d 01h /or1k/tags/stable_0_2_0/
1613 change default phoenix 6802d 10h /or1k/tags/stable_0_2_0/
1612 major optimizations for or32 target phoenix 6802d 11h /or1k/tags/stable_0_2_0/
1610 Update ChangeLog nogj 6805d 12h /or1k/tags/stable_0_2_0/
1609 0.2.0-rc2 release nogj 6805d 13h /or1k/tags/stable_0_2_0/
1608 Avoid scheduleing too many jobs, potentially underflowing the scheduler stack nogj 6806d 07h /or1k/tags/stable_0_2_0/
1607 Don't drop cycles from the scheduler nogj 6806d 07h /or1k/tags/stable_0_2_0/
1606 fix uninitialized reads phoenix 6806d 12h /or1k/tags/stable_0_2_0/
1605 Execute l.ff1 instruction nogj 6813d 07h /or1k/tags/stable_0_2_0/
1604 Fix dumphex/dumpverilog to not do unaligned memory access nogj 6813d 07h /or1k/tags/stable_0_2_0/

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