URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0/] - Rev 412

Rev	Log message	Author	Age	Path
390	Changed instantiation name of VS RAMs.	lampret	8293d 05h	/or1k/tags/stable_0_2_0/
389	Changed default delay for load and store in superscalar cpu.	lampret	8293d 05h	/or1k/tags/stable_0_2_0/
388	Added comments for cpu section.	lampret	8293d 05h	/or1k/tags/stable_0_2_0/
387	Now FPGA and ASIC target are separate.	lampret	8293d 07h	/or1k/tags/stable_0_2_0/
386	Fixed VS RAM instantiation - again.	lampret	8293d 07h	/or1k/tags/stable_0_2_0/
385	check testbench now modified to work with new report output	markom	8293d 13h	/or1k/tags/stable_0_2_0/
384	modified simmem.cfg structure! ADD > BEFORE EACH LINE!	markom	8293d 14h	/or1k/tags/stable_0_2_0/
383	modified simmem.cfg structure! ADD	markom	8293d 14h	/or1k/tags/stable_0_2_0/
382	bitmask function bug fixed	markom	8293d 16h	/or1k/tags/stable_0_2_0/
381	number display is more strict with 0x prefix with hex numbers	markom	8293d 16h	/or1k/tags/stable_0_2_0/