URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0/] - Rev 415

Rev	Log message	Author	Age	Path
394	dependency joined with dependstats; history moved to sim section	markom	8263d 21h	/or1k/tags/stable_0_2_0/
393	messages: exception on many places changed to abort	markom	8263d 22h	/or1k/tags/stable_0_2_0/
391	Fixed except_stop width and fixed EX PC for 1400444f no-ops.	lampret	8264d 05h	/or1k/tags/stable_0_2_0/
390	Changed instantiation name of VS RAMs.	lampret	8264d 07h	/or1k/tags/stable_0_2_0/
389	Changed default delay for load and store in superscalar cpu.	lampret	8264d 07h	/or1k/tags/stable_0_2_0/
388	Added comments for cpu section.	lampret	8264d 07h	/or1k/tags/stable_0_2_0/
387	Now FPGA and ASIC target are separate.	lampret	8264d 09h	/or1k/tags/stable_0_2_0/
386	Fixed VS RAM instantiation - again.	lampret	8264d 09h	/or1k/tags/stable_0_2_0/
385	check testbench now modified to work with new report output	markom	8264d 15h	/or1k/tags/stable_0_2_0/
384	modified simmem.cfg structure! ADD > BEFORE EACH LINE!	markom	8264d 16h	/or1k/tags/stable_0_2_0/