URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0/] [or1ksim/] [peripheral/] - Rev 670

Rev	Log message	Author	Age	Path
492	uart THRE interrupt immedialty after write to IER	markom	8269d 10h	/or1k/tags/stable_0_2_0/or1ksim/peripheral/
490	clkcycle parsing problem fixed	markom	8270d 06h	/or1k/tags/stable_0_2_0/or1ksim/peripheral/
483	Implemented some GPIO tests	erez	8271d 02h	/or1k/tags/stable_0_2_0/or1ksim/peripheral/
477	Improved multi-id vapi logs (i.e. GPIO)	erez	8271d 06h	/or1k/tags/stable_0_2_0/or1ksim/peripheral/
445	Reading GPIO input reg now also returns values on output bits	erez	8277d 13h	/or1k/tags/stable_0_2_0/or1ksim/peripheral/
444	Added GPIO simulation	erez	8277d 22h	/or1k/tags/stable_0_2_0/or1ksim/peripheral/
439	Added "fake" JTAG proxy log to vapi log file	erez	8278d 06h	/or1k/tags/stable_0_2_0/or1ksim/peripheral/
424	memory configuration file joined into .cfg file; *mem.cfg are obsolete; read-only and write-only memory is supported; memory logging is not yet supported; update of testbench - only cache test fails, since it writes to RO memory	markom	8279d 10h	/or1k/tags/stable_0_2_0/or1ksim/peripheral/
423	changed break behaviour and interrupt pending; interrupt line chabnged to 15; sync bug in mode switch	markom	8280d 05h	/or1k/tags/stable_0_2_0/or1ksim/peripheral/
418	Renamed ethernet's RX_BD_NUM to TX_BD_NUM (following change in original files)	erez	8280d 23h	/or1k/tags/stable_0_2_0/or1ksim/peripheral/