URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc1/] - Rev 1244

Rev	Log message	Author	Age	Path
1196	removed second debug/Makefile (credits: Daniel Wiklund - danwi@isy.liu.se)	dries	7595d 16h	/or1k/tags/stable_0_2_0_rc1/
1195	made the project file a little bit more universal	dries	7595d 18h	/or1k/tags/stable_0_2_0_rc1/
1194	correct all the syntax errors	dries	7595d 18h	/or1k/tags/stable_0_2_0_rc1/
1193	disabled SRAM_GENERIC and added comment + corrected 'wb_err' into 'wb_err_o'	dries	7595d 18h	/or1k/tags/stable_0_2_0_rc1/
1192	disabled 'bench_defines.v' during synthesis + added define to specify usage of flash instruction address	dries	7595d 19h	/or1k/tags/stable_0_2_0_rc1/
1191	disabled 'bench_defines.v' during synthesis + added define to specify usage of flash instruction address	dries	7595d 19h	/or1k/tags/stable_0_2_0_rc1/
1188	Added support for rams with byte write access.	simons	7611d 18h	/or1k/tags/stable_0_2_0_rc1/
1186	Added support for rams with byte write access.	simons	7612d 17h	/or1k/tags/stable_0_2_0_rc1/
1184	Scan signals mess fixed.	simons	7619d 10h	/or1k/tags/stable_0_2_0_rc1/
1183	OpenRISC port of gdb-5.3 straightforwardly derived from gdb-5.0	sfurman	7624d 02h	/or1k/tags/stable_0_2_0_rc1/