OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc1/] - Rev 1558

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
1538 Speed up the immu nogj 6933d 09h /or1k/tags/stable_0_2_0_rc1/
1537 Remove old spr logging code. Use `-d +spr' to get spr access logged to stderr nogj 6933d 09h /or1k/tags/stable_0_2_0_rc1/
1536 Add README.or32 robertmh 6934d 16h /or1k/tags/stable_0_2_0_rc1/
1534 Import of Glibc robertmh 6934d 17h /or1k/tags/stable_0_2_0_rc1/
1533 Add missing newline at EOF robertmh 6935d 15h /or1k/tags/stable_0_2_0_rc1/
1532 Add pretty spr dumping code nogj 6936d 19h /or1k/tags/stable_0_2_0_rc1/
1531 Remove non-trigerable out-of-range checks nogj 6936d 19h /or1k/tags/stable_0_2_0_rc1/
1530 Move the checking of the debug channel into the TRACE() macro nogj 6936d 19h /or1k/tags/stable_0_2_0_rc1/
1529 * The effective address as written to the I/DCBPR registers needs to be translated by the respective mmu.
* Don't treat any values as special in the handling of DCPBR, DCBFR, DCBIR, ICBPR and ICBIR.
nogj 6937d 21h /or1k/tags/stable_0_2_0_rc1/
1528 s/HAS_ISBLANK/HAVE_ISBLANK/ fix compileing on windows/cygwin. Reported by Kuoping Hsu and Girish Venkatar nogj 6938d 04h /or1k/tags/stable_0_2_0_rc1/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.