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[/] [or1k/] [tags/] [stable_0_2_0_rc1/] [or1ksim/] - Rev 128

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Rev Log message Author Age Path
79 Data and instruction cache simulation added. lampret 8555d 15h /or1k/tags/stable_0_2_0_rc1/or1ksim/
78 (i/d)tlb_status lampret 8679d 05h /or1k/tags/stable_0_2_0_rc1/or1ksim/
77 Regular update. lampret 8679d 05h /or1k/tags/stable_0_2_0_rc1/or1ksim/
76 regular update lampret 8679d 05h /or1k/tags/stable_0_2_0_rc1/or1ksim/
75 simgetstr added. eval_mem32 replaced with evalsim_mem32. lampret 8679d 05h /or1k/tags/stable_0_2_0_rc1/or1ksim/
74 Same as DMMU. lampret 8686d 04h /or1k/tags/stable_0_2_0_rc1/or1ksim/
73 Fixed all bugs. Now more or less works. IMMU still has some problems (exception start). lampret 8686d 04h /or1k/tags/stable_0_2_0_rc1/or1ksim/
72 Added 'how to build GNU tools' lampret 8691d 05h /or1k/tags/stable_0_2_0_rc1/or1ksim/
69 Sim debug. lampret 8698d 05h /or1k/tags/stable_0_2_0_rc1/or1ksim/
68 Added hook for l.sys 204. Changed SPR of flag (no more CCR) lampret 8698d 05h /or1k/tags/stable_0_2_0_rc1/or1ksim/

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