URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc1/] [or1ksim/] - Rev 1480

Rev	Log message	Author	Age	Path
1448	Issue an error if the selected target cpu is unknown	nogj	7025d 13h	/or1k/tags/stable_0_2_0_rc1/or1ksim/
1446	Cosmetic fixes	nogj	7025d 13h	/or1k/tags/stable_0_2_0_rc1/or1ksim/
1444	Move the definitions needed for the simple execution model out of or32.h and into simpl32_defs.h	nogj	7025d 13h	/or1k/tags/stable_0_2_0_rc1/or1ksim/
1442	Replace some problematic calles to mfspr/mtspr with direct access to the spr	nogj	7025d 13h	/or1k/tags/stable_0_2_0_rc1/or1ksim/
1440	Reclasify l.trap and l.sys to be an exception instruction	nogj	7025d 13h	/or1k/tags/stable_0_2_0_rc1/or1ksim/
1438	NOP_REPORT should report numbers in hex not decimal	nogj	7025d 13h	/or1k/tags/stable_0_2_0_rc1/or1ksim/
1436	Rearange some code to make it clearer what it does	nogj	7025d 13h	/or1k/tags/stable_0_2_0_rc1/or1ksim/
1434	Fix the prototype of setsim_reg	nogj	7025d 13h	/or1k/tags/stable_0_2_0_rc1/or1ksim/
1432	Collect most of the cpu state variables in a structure (cpu_state)	nogj	7025d 13h	/or1k/tags/stable_0_2_0_rc1/or1ksim/
1430	Log SPR_SR in the execution log	nogj	7025d 13h	/or1k/tags/stable_0_2_0_rc1/or1ksim/