URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc1/] [or1ksim/] - Rev 689

Rev	Log message	Author	Age	Path
643	Quick bug fix.	ivang	8253d 10h	/or1k/tags/stable_0_2_0_rc1/or1ksim/
642	Modified logging of SPR accesses. Logging only explicit instruction accesses.	ivang	8253d 10h	/or1k/tags/stable_0_2_0_rc1/or1ksim/
641	Modified logging of SPR accesses. Logging only explicit instruction accesses.	ivang	8253d 11h	/or1k/tags/stable_0_2_0_rc1/or1ksim/
640	Merge profiler and mprofiler with sim.	ivang	8253d 12h	/or1k/tags/stable_0_2_0_rc1/or1ksim/
639	MMU cache inhibit bit test added.	simons	8256d 03h	/or1k/tags/stable_0_2_0_rc1/or1ksim/
638	TLBTR CI bit is now working properly.	simons	8256d 03h	/or1k/tags/stable_0_2_0_rc1/or1ksim/
633	Bug fix in command line parser.	ivang	8257d 08h	/or1k/tags/stable_0_2_0_rc1/or1ksim/
632	profiler and mprofiler merged into sim.	ivang	8258d 03h	/or1k/tags/stable_0_2_0_rc1/or1ksim/
631	Real cache access is simulated now.	simons	8259d 02h	/or1k/tags/stable_0_2_0_rc1/or1ksim/
630	some bug fixes in store buffer analysis	markom	8259d 11h	/or1k/tags/stable_0_2_0_rc1/or1ksim/