URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc1/] [or1ksim/] [cache/] - Rev 1555

Rev	Log message	Author	Age	Path
970	Testbench is now running on ORP architecture platform.	simons	7985d 01h	/or1k/tags/stable_0_2_0_rc1/or1ksim/cache/
884	code cleaning - a lot of global variables moved to runtime struct	markom	8021d 13h	/or1k/tags/stable_0_2_0_rc1/or1ksim/cache/
876	Beta release of ATA simulation	rherveille	8029d 00h	/or1k/tags/stable_0_2_0_rc1/or1ksim/cache/
638	TLBTR CI bit is now working properly.	simons	8180d 02h	/or1k/tags/stable_0_2_0_rc1/or1ksim/cache/
631	Real cache access is simulated now.	simons	8183d 01h	/or1k/tags/stable_0_2_0_rc1/or1ksim/cache/
626	store buffer added	markom	8183d 14h	/or1k/tags/stable_0_2_0_rc1/or1ksim/cache/
541	lot of new parameters concerning memory delays added; bpb parameter moved from cpu to new bpb section; UPDATE YOUR .CFG FILES!	markom	8204d 10h	/or1k/tags/stable_0_2_0_rc1/or1ksim/cache/
517	some performance optimizations	markom	8208d 09h	/or1k/tags/stable_0_2_0_rc1/or1ksim/cache/
500	Added .cvsignore files for annoying generated files	erez	8210d 13h	/or1k/tags/stable_0_2_0_rc1/or1ksim/cache/
429	cache configuration added	markom	8232d 09h	/or1k/tags/stable_0_2_0_rc1/or1ksim/cache/