URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc1/] [or1ksim/] [cache/] - Rev 1765

Rev	Log message	Author	Age	Path
1085	Bug fixed.	simons	7869d 10h	/or1k/tags/stable_0_2_0_rc1/or1ksim/cache/
997	PRINTF should be used instead of printf; command redirection repaired	markom	7958d 23h	/or1k/tags/stable_0_2_0_rc1/or1ksim/cache/
992	A bug when cache enabled and bus error comes fixed.	simons	7960d 15h	/or1k/tags/stable_0_2_0_rc1/or1ksim/cache/
970	Testbench is now running on ORP architecture platform.	simons	7966d 10h	/or1k/tags/stable_0_2_0_rc1/or1ksim/cache/
884	code cleaning - a lot of global variables moved to runtime struct	markom	8002d 21h	/or1k/tags/stable_0_2_0_rc1/or1ksim/cache/
876	Beta release of ATA simulation	rherveille	8010d 09h	/or1k/tags/stable_0_2_0_rc1/or1ksim/cache/
638	TLBTR CI bit is now working properly.	simons	8161d 11h	/or1k/tags/stable_0_2_0_rc1/or1ksim/cache/
631	Real cache access is simulated now.	simons	8164d 10h	/or1k/tags/stable_0_2_0_rc1/or1ksim/cache/
626	store buffer added	markom	8164d 23h	/or1k/tags/stable_0_2_0_rc1/or1ksim/cache/
541	lot of new parameters concerning memory delays added; bpb parameter moved from cpu to new bpb section; UPDATE YOUR .CFG FILES!	markom	8185d 19h	/or1k/tags/stable_0_2_0_rc1/or1ksim/cache/