URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc1/] [or1ksim/] [cpu/] - Rev 1308

Rev	Log message	Author	Age	Path
1169	Added support for l.addc instruction.	csanchez	7715d 17h	/or1k/tags/stable_0_2_0_rc1/or1ksim/cpu/
1150	remove unneded include	phoenix	7795d 22h	/or1k/tags/stable_0_2_0_rc1/or1ksim/cpu/
1117	Ignore generated files for CVS purposes	sfurman	7839d 14h	/or1k/tags/stable_0_2_0_rc1/or1ksim/cpu/
1114	Added cvs log keywords	lampret	7870d 09h	/or1k/tags/stable_0_2_0_rc1/or1ksim/cpu/
1106	Cache invalidate bug fixed again (it was ok before).	simons	7919d 21h	/or1k/tags/stable_0_2_0_rc1/or1ksim/cpu/
1097	Cache invalidate bug fixed.	simons	7926d 16h	/or1k/tags/stable_0_2_0_rc1/or1ksim/cpu/
1086	STACK_ARGS is getting obsolete and is only needed by simprintf, which needs it to be 0.	lampret	7933d 12h	/or1k/tags/stable_0_2_0_rc1/or1ksim/cpu/
1061	ELF sym loading improved	markom	7979d 23h	/or1k/tags/stable_0_2_0_rc1/or1ksim/cpu/
1049	Added "breaks" command that prints all set breakpoints.	ivang	8006d 20h	/or1k/tags/stable_0_2_0_rc1/or1ksim/cpu/
1034	Fixed encoding for l.div/l.divu.	lampret	8012d 10h	/or1k/tags/stable_0_2_0_rc1/or1ksim/cpu/