URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc1/] [or1ksim/] [mmu/] - Rev 1117

Rev	Log message	Author	Age	Path
425	immu and dmmu configurations added	markom	8234d 19h	/or1k/tags/stable_0_2_0_rc1/or1ksim/mmu/
416	IMMU bugs fixed.	simons	8237d 08h	/or1k/tags/stable_0_2_0_rc1/or1ksim/mmu/
344	added acv test for uart; sim debug now has verbose levels; lot of bugs fixed in uart model	markom	8261d 20h	/or1k/tags/stable_0_2_0_rc1/or1ksim/mmu/
221	major changes to testbench; debug unit is moved to /debug; memory organization can be customized; UART from simons; overall cleanup	markom	8282d 21h	/or1k/tags/stable_0_2_0_rc1/or1ksim/mmu/
204	Added function prototypes to stop gcc from complaining	erez	8316d 18h	/or1k/tags/stable_0_2_0_rc1/or1ksim/mmu/
167	- SPR values corrected - testbenches now work - lot of optimizations, use --disable-debugmod for optimal performance - some tick timer bugs fixed	markom	8359d 17h	/or1k/tags/stable_0_2_0_rc1/or1ksim/mmu/
102	Major update to include PM, PIC, Cache Mngmnt and non-interactive mode.	lampret	8442d 03h	/or1k/tags/stable_0_2_0_rc1/or1ksim/mmu/
74	Same as DMMU.	lampret	8648d 23h	/or1k/tags/stable_0_2_0_rc1/or1ksim/mmu/
73	Fixed all bugs. Now more or less works. IMMU still has some problems (exception start).	lampret	8648d 23h	/or1k/tags/stable_0_2_0_rc1/or1ksim/mmu/
62	OR1K DMMU model.	lampret	8661d 00h	/or1k/tags/stable_0_2_0_rc1/or1ksim/mmu/