URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc1/] [or1ksim/] [testbench/] - Rev 541

Rev	Log message	Author	Age	Path
485	gdb.h moved to debug dir; except.ld renamed to default.ld	markom	8274d 06h	/or1k/tags/stable_0_2_0_rc1/or1ksim/testbench/
484	Changed to support execution from various addresses.	simons	8274d 18h	/or1k/tags/stable_0_2_0_rc1/or1ksim/testbench/
483	Implemented some GPIO tests	erez	8274d 18h	/or1k/tags/stable_0_2_0_rc1/or1ksim/testbench/
480	RTL_SIM define added for shorter simulation runtime.	simons	8274d 22h	/or1k/tags/stable_0_2_0_rc1/or1ksim/testbench/
479	connection with gdb repaired; temp_except_delay removed; lot of except and debug code cleaned; sys 203 causes stall under gdb; non-sim memory area log bug fixed	markom	8274d 22h	/or1k/tags/stable_0_2_0_rc1/or1ksim/testbench/
478	Started adding acv_gpio testbench	erez	8274d 23h	/or1k/tags/stable_0_2_0_rc1/or1ksim/testbench/
476	Fixed warnings.	ivang	8274d 23h	/or1k/tags/stable_0_2_0_rc1/or1ksim/testbench/
475	l.jalr r9 is not used any more.	simons	8275d 00h	/or1k/tags/stable_0_2_0_rc1/or1ksim/testbench/
473	Added test flag templates.	ivang	8275d 04h	/or1k/tags/stable_0_2_0_rc1/or1ksim/testbench/
472	Removed MC initialization. Must be done in except_mc.S	ivang	8275d 04h	/or1k/tags/stable_0_2_0_rc1/or1ksim/testbench/