URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc2/] - Rev 634

Rev	Log message	Author	Age	Path
613	init: trap exception occurs always; initialization of sr not needed anymore	markom	8205d 21h	/or1k/tags/stable_0_2_0_rc2/
612	Tick timer period extended to meet real timing.	simons	8205d 23h	/or1k/tags/stable_0_2_0_rc2/
611	EEAR register is not changed by trap, sys, int, tick and range exception.	simons	8207d 00h	/or1k/tags/stable_0_2_0_rc2/
610	Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.	lampret	8207d 00h	/or1k/tags/stable_0_2_0_rc2/
609	Added wb_err_o to flash and sram i/f for testing the buserr exception.	lampret	8207d 00h	/or1k/tags/stable_0_2_0_rc2/
608	Range exception removed from test.	simons	8207d 20h	/or1k/tags/stable_0_2_0_rc2/
607	single step steps just one instruction ^c bug fixed	markom	8207d 20h	/or1k/tags/stable_0_2_0_rc2/
606	raw register range bug fixed; acv_uart test passes	markom	8208d 20h	/or1k/tags/stable_0_2_0_rc2/
605	simulator prints out a message, when gdb is not attached and stall occurs; OV flag fixed	markom	8208d 20h	/or1k/tags/stable_0_2_0_rc2/
604	mul test repaired - signed multiplication; obsolete pic test removed; make check pass	markom	8208d 21h	/or1k/tags/stable_0_2_0_rc2/