OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc2/] [or1ksim/] - Rev 321

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
270 some speedups, when debug module is disabled markom 8302d 23h /or1k/tags/stable_0_2_0_rc2/or1ksim/
269 added labels; corrected false if clause, preventing to fill iqueue markom 8302d 23h /or1k/tags/stable_0_2_0_rc2/or1ksim/
264 updated cpu config section; added sim config section markom 8305d 16h /or1k/tags/stable_0_2_0_rc2/or1ksim/
263 configure for cpu; modified command line options markom 8305d 17h /or1k/tags/stable_0_2_0_rc2/or1ksim/
262 small bug in build_automata fixed; configure for memory markom 8305d 18h /or1k/tags/stable_0_2_0_rc2/or1ksim/
261 modified memory accesses; added cfg script; added pic test basic entry of vga; some extensions to mc markom 8305d 20h /or1k/tags/stable_0_2_0_rc2/or1ksim/
260 Replaced some 8-bit memory access with 32-bit erez 8307d 10h /or1k/tags/stable_0_2_0_rc2/or1ksim/
259 Removed tick/Makefile, which is generated anyway erez 8307d 13h /or1k/tags/stable_0_2_0_rc2/or1ksim/
258 Added Ethernet test; renamed dma to dmatest; commented out missing pic.c erez 8307d 13h /or1k/tags/stable_0_2_0_rc2/or1ksim/
257 Added initial Ethernet simulation (only TX as yet) erez 8307d 13h /or1k/tags/stable_0_2_0_rc2/or1ksim/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.